05-31-2010 12:04 AM
I have generated the FIFO with the following setting
FIFO works fine when fifo_rd_en and fifo_wr_en are given with the same signal....
The data in to FIFO is at a slower rate when compared to FIFO_clk and data_out is read at FIFO_clk
For this ,
1) I have given the wr_en with a slower clk , even though FIFO clk is higher ...
2) I have checked the if data_count is greater than 500 and then rd_en is made high
3) After reading 256 datas I have made rd_en=0
While the fifo_rd_en = high , I find the values read from the fifo ,
0- 1A = remains 00000000
1B- 39 = some values(hopefully from fifo)
above 40 to 255 = remains zero....
Why does this happen ? Any reasons?
06-05-2010 06:18 AM
I have several questions for you:
1. Are you experiencing this in simulation or hardware?
2. Have you tried your same test with a newer version of the core; ie v6.1
3. Why are you using a common clock BRAM configuration if you're using two different clocks for your read and write data?