When moved to ISE11.5, I've noticed, that there is no lines like these
// XST black box declaration // box_type "black_box" // synthesis attribute box_type of <unit> is "black_box"
added to Verilog simulation file. This leads to lot of warnings about instantiating black boxes. With ISE7.1 it seems that mentioned attributes were added automatically.
Anyone met same behaviour? Just in case, contents of .cpg file is:
SET addpads = False SET asysymbol = True SET busformat = BusFormatAngleBracketNotRipped SET createndf = False SET designentry = Verilog SET device = xc3s5000 SET devicefamily = spartan3 SET flowvendor = Foundation_ISE SET formalverification = False SET foundationsym = False SET implementationfiletype = Ngc SET package = fg900 SET removerpms = False SET simulationfiles = Behavioral SET speedgrade = -5 SET verilogsim = True SET vhdlsim = False SET workingdirectory = .\tmp\