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rrlagic
Explorer
Explorer
10,470 Views
Registered: ‎06-15-2010

Coregen does not insert box_type

Hello!

When moved to ISE11.5, I've noticed, that there is no lines like these

 

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of <unit> is "black_box"

 

added to Verilog simulation file. This leads to lot of warnings about instantiating black boxes. With ISE7.1 it seems that mentioned attributes were added automatically.

 

Anyone met same behaviour? Just in case, contents of .cpg file is:

 

SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = Verilog
SET device = xc3s5000
SET devicefamily = spartan3
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg900
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -5
SET verilogsim = True
SET vhdlsim = False
SET workingdirectory = .\tmp\

 

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luisb
Xilinx Employee
Xilinx Employee
10,403 Views
Registered: ‎04-06-2010

These warnings should not show up in simulation; they should show up during synthesis.

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