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Observer
Observer
1,484 Views
Registered: ‎09-08-2016

Cortex-M Processors on FPGA

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Hi

When I've tried to open the block design in Vivado I got these errors

 [BD 41-1712] The specified IP 'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'
 [BD 41-595] Failed to add BD cell <axi_bram_ctrl_0>
 [BD 41-1157] Failed to parse Design <m1_for_arty_a7> from BD file </home/eexma67/Downloads/ARM_M1/hardware/m1_for_arty_a7/block_diagram/m1_for_arty_a7.bd>
 [BD 41-425] Failed to read Diagram <m1_for_arty_a7> from BD file </home/eexma67/Downloads/ARM_M1/hardware/m1_for_arty_a7/block_diagram/m1_for_arty_a7.bd>

and I follow the instructions.

 

Thank you.

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Adventurer
Adventurer
1,435 Views
Registered: ‎12-16-2018
OK, I'M Vivado 2017.4 in Windows and everything works fine to me. I hope that you complete your design with this kind of processor in your FPGA

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Adventurer
Adventurer
1,451 Views
Registered: ‎12-16-2018

Hi 

The problem seem to be related with the fact that the Cortex M for Arty FPGA was designed for another different part. I test the BRAM controller 4.0 in the FPGA that you show in the error text and Vivado doesn't throws any error. This suggest that the problem could be related with your source design. If you are interested in use a micro controller in your FPGA you can use the Microblaze. Maybe you know already that. I hope that this response be helpful to you

BD_PROBLEM.png
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Observer
Observer
1,445 Views
Registered: ‎09-08-2016

Hi

thank u so much for ur reply. I would like to test it. I faced this problem just with I run Vivado on Linux but on windows it work fine.

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Adventurer
Adventurer
1,436 Views
Registered: ‎12-16-2018
OK, I'M Vivado 2017.4 in Windows and everything works fine to me. I hope that you complete your design with this kind of processor in your FPGA

View solution in original post

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