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acc-iot
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Registered: ‎09-07-2020

Create verilog simulation file with Block Memory Generator 8.4

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Hello,

I am working under Vivado v.2020.01. I have generated a RAM with the Block Memory Generator 8.4, and when I look into the ip output folder, I can only see a blk_mem_gen_0_stub.v verilog file, and a blk_mem_gen_0.veo file, which are only for instanciation purposes, not simulation purposes.

I can see in the header of the stub file that it was generated by some internal command of blk_mem_gen : write_verilog -mode synth_stub.

Is there any way for me to generate a complete verilog simulation model of my memory ?

Thanks,

Alex

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acc-iot
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Registered: ‎09-07-2020

Hello zhangfeng,

Thanks for your answer. I have found the necessary verilog simulation files for the generated RAM block as follows:

- myproject.srcs/sources_1/ip/myRAM/sim/myRAM.v

- myproject.srcs/sources_1/ip/myRAM/simulation/blk_mem_gen_v8_4.v

With these files,I can now run simulation outside of Vivado environment, with another vendor simulator which was my initial target.

My problem is solved

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zhangfeng
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Registered: ‎10-29-2016

Hello, @acc-iot .

 

Use the file under the "simulation" folder.

 

If there are undefined modules in that file,

comile your own simulation libraries by choosing "Compile Simulation Libraries..." under "Tools" in Vivado.

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acc-iot
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Registered: ‎09-07-2020

Hello zhangfeng,

Thanks for your answer. I have found the necessary verilog simulation files for the generated RAM block as follows:

- myproject.srcs/sources_1/ip/myRAM/sim/myRAM.v

- myproject.srcs/sources_1/ip/myRAM/simulation/blk_mem_gen_v8_4.v

With these files,I can now run simulation outside of Vivado environment, with another vendor simulator which was my initial target.

My problem is solved

View solution in original post

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