Data width supported with Byte wide writes and "write_first" in TDP XPM RAM?

[waidcsuf]

UG953 states:

NOTE: When byte wide writes are enabled on port [A|B] and the write mode is set to

“no_change”, the maximum WRITE_DATA_WIDTH_[A|B] supported is

•32/36 when the MEMORY_PRIMITIVE attribute is set to “block”

•64/72 when the MEMORY_PRIMTIVE attribute is set to “ultra”

But what about when I am NOT using "no_change"?  I need the data width to be 128 and I'm getting a synth error about the width.

[pthakare]

Hi @waidcsuf 

Write_first is only supported when Memory Primitive is set to  "Block"

and allowable Width for WRITE_DATA_WIDTH _A/B is 1 to 4608.

Please check if you are selecting the Memory primitive to "Block" in your macro instatiation.

Additonally The values of WRITE_DATA_WIDTH_A and READ_DATA_WIDTH_A must be equal.

When ECC is enabled and set to "encode_only" or "both_encode_and_decode", then WRITE_DATA_WIDTH_A has to be multiples of 64-bits When ECC is enabled and set to "decode_only", then WRITE_DATA_WIDTH_A has to be multiples of 72-bits

[waidcsuf]

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Additonally The values of WRITE_DATA_WIDTH_A and READ_DATA_WIDTH_A must be equal.

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What about if DATA_WIDTH_A /= DATA_WIDTH_B? Can those be different with the following criteria?

1. XPM set to Block ram
2. WRITE_MODE = WRITE_FIRST
3. BYTE_WRITE_WIDTH_A = WRITE_DATA_WIDTH_A = 128
4. DATA_WIDTH_B = 64

[pthakare · Accepted solution]

Hi @waidcsuf 

This is Supported . Only the DATA_WIDTH for same port either A or B must be same.

[pthakare]

Hi @waidcsuf 

Did you get a chance to modify the instatiation as suggested ?  Please let us know if you have further queries around this.