Disabling AXI Stream FIFO receive using RDFR

[ewalls]

Vivado 18.3, AXI Stream FIFO v4.2

I have an application where I have constant data coming in on the receive stream interface from an external device.  The data is coming in at about 20KHz.

I have an external signal that when asserted means the data on the stream is valid and should be passed to the PS but not at any other times.  I could use this signal to gate the TValid on the stream interface however reading the datasheet there is a register called Recieve Data FIFO Reset Register (RDFR) that I thought I could use.  I've tried writing 0xA5 to this register thinking it would place and hold the receive FIFO in reset until I write over the 0xA5 value.  However this doesn't seem to be what happens.

Question: Does writing 0xA5 to the RDFR register just force a reset and release or should writing 0xA5 put the receive FIFO in reset and keep it there until a none 0xA5 value is written?

[drjohnsmith]

I dont know,

but this is interesting

https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf

"

This reset will not occur until receive activity on the RX AXI Stream has completed. Only during inactive times on the RX AXI Stream can a reset occur. It will affect only the receive circuitry in this core. This prevents the core on the other end of the AXI4-Stream from transmitting a partial packet which can cause failure condition in that core.

Because of this mode of operation, it is possible that if the AXI4-Stream interface becomes unresponsive during an AXI4-Stream transaction, that the reset will never occur. For example, if a packet is received over the AXI4-Stream that exceeds the FIFO size of this core, the core destination is ready to become inactive in the middle of a transfer. In this case, an S_AXI_ARESETN reset is needed.

"

[ewalls]

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This reset will not occur until receive activity on the RX AXI Stream has completed. Only during inactive times on the RX AXI Stream can a reset occur. It will affect only the receive circuitry in this core. This prevents the core on the other end of the AXI4-Stream from transmitting a partial packet which can cause failure condition in that core.

I don't really understand what this means.

I am transfering 1 x 32 bit word at a rate of 20KHz so the bus is sitting inactive for a very long time.  The clock driving the FIFO is about 12MHz.

So does that mean that the FIFO receive should go into reset in between one of the single word transfers? 

The datasheet is not very clear.

[drjohnsmith]

in lue of a good data sheet

I drop back to simulation