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GorkaFraunhofer

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09-02-2020 05:41 AM

408 Views

Registered:
03-06-2020

FFT FPGA Output

Good day all,

I am currently using the Xilinx FFT IP block, with an AXI-Stream sample sequence incoming (first column in the attached mat file). I have several doubts and question, hope any of you can answer them.The input is a counter for both imaginary and real parts up to 512 samples.

The 1st one is related to the configuration stream that comes in into the block. I have tried, and checked with the ILA, the configuration parameters described in the user guide. Now, if I have a 512-FFT with no cyclic prefix, and [ 1 1 1 1 1 1 1 1 2] scale stages, I assume, I will get something like configBits = 0b0001 0101 0101 0101 0110 00000001 00001001. However, when I set this and pull it through AXI DMA MM2S (since I stored this in the DDR), I get a wrong output result (compared to what Matlab gives - 2nd column). Moreover, I got 'proper' output when I sent or fixed the configBits = 0x0000 0000. How is this possible? How do I need to feed the Configuration channel of the FFT IP block?

The 2nd one is related to the order of the output. If I do not flip (on Matlab) the output FFT result of the block, I can not see the output values to be similar (on both Matlab and FPGA). Also, There is some weird output delay, I do not know how to describe it, between what I got with Matlab and FPGA. Does the FPGA give DC first? is the last sample in the ILA the first processed by the core? The columns in the mat file are 2nd Matlab FFT-output; 3rd the FPGA FFT output but flipped, and 4th output of the FPGA FFT without being flipped. Notice the delay between the FPGA and Matlab output of 1 output sample (in the mat file).

The 3rd question is about how to improve the FPGA FFT output, since it seems still not similar enough to Matlab output. When trying to inverse (IFFT) the output (on Matlab with FPGA FFT output), to get the FPGA FFT input, I did not get the input provided to the FPGA FFT. Which parameters would be here important?

I have also added the mat file in pdf format. And the FFT configuration.:

Parameter | Value |

Num of channels | 1 |

FFT length | 512 |

Architecture | Radix-2, Burst I/O |

Data format | Fixed Point |

Scaling option | Scaled |

Rounding mode | Truncation |

Precision | Input data width (auto): 16 - Phase factor width: 16 |

Throttle | Non Real Time |

1 Reply

GorkaFraunhofer

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09-08-2020 02:49 AM

313 Views

Registered:
03-06-2020

Hello all,

I have been checking again the FFT Xilinx documentation, and read carefully all the descriptions that are written. I came across several points that fixed and solved my questions 1 to 3 (all related to fixing one detail fixed the next problem, and so). I added the answers to the questions, so if everyone falls into the same error, she/he can fix it.

According to the documentation, there is always a must of setting the FFT IP configuration registers through the Configuration Channel. Now, in my case, I have used a DMA accessing a DDR (and set by the arm processor) for configuration. What I needed to transfer (which is not the 0x00000000 commented above) is dependent on the configuration given in the Block Design step. Since I do not need change the point size, I skip this field (which it is written in table 3-3 of the documentation as *"... this filed is only present with run time configurable..."*). Also, skipping the cyclic prefix due to unchecking the box in the BD step. That left me with 2 fields, which are FFT direction and scaling. I also noticed that the bit width of the stream is 24 bits long, which does not represent all my scale and FWD FFT field widths. Be aware of the "sending" method when configuring the FFT. It admits only 24 bits field, always sent as MSB first; as opposed to what I assumed to be sent first. In my case, with FWD FFT and [1 0 1 0 1 0 1 0 2], I get 0x01111201; which needed to be split into two values config[0] = 0x00000001 and config[1] = 0x00111201 (note the order of array and extension due to DMA - DDR communication).

Thus, all that matters is the field order, size and BD configuration (and a thorough reading of the FFT documentation). Correcting these, made 2nd and 3rd point work. Now, I have attached comparison of Matlab FFT output and FPGA FFT output (which can not be really comparable since the FFT used on MATLAB is floating point and FPGA is fixed point). Nevertheless, I think, I have come to a solution that needs a little bit further tuning (I attach the comparison outcome). The inputs to the FFT are the same (integer values of 16 bits long I and 16b Q). Could anyone explain the situation in the FFT max peak? I will continue researching. The input is a windowed (Blackmann) counter (0+0i, 1+1i, ..., N+Ni). Problem might well be with the window method, but I see the same output in both Matlab windowed samples and FPGA windowed samples.

Best Regards,

Gorka Iturbe