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pvanecek
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Registered: ‎12-07-2010

FIFO Generator V4.4 stuck Full and Almost Full signals

I have a single clock, block RAM, First Word Fall Through (FWFT) FIFO generated on ISE 10.1.03 and FIFO core generator 4.4. I have observed that when the FIFO gets filled we get stuck bits on both the Full and Almost Full flags and it is unable to recover after a rese. (They remain high)

 

I saw a similar issue in the forums and they suggested updating ISE as it was a known issue. http://forums.xilinx.com/t5/System-Logic/Xilinx-FIFO-Core-generator-FULL-EMPTY-signal-path/td-p/95504.

 

Unfortunately I can't update the project from ISE 10.1, but I do have a version of 13.1 available to me. Is it possible to use the 13.1 Fifo Core generator and import the .xco/ngc files back into 10.1.?

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pvanecek
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Registered: ‎12-07-2010

Haven't heard anything from anyone on this. My fix was to build my own 'Almost Full' flag at a value less than Almost full and use that to gate the write line - preventing the Full or Almost Full flags from ever sticking. Works well and I continue to use the Core Generator 4.4.

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