09-30-2008 08:29 PM
Hi All -
I'm experiencing some very odd problems with a CoreGen FIFO. The write clock is running at 125 MHz and the read clock at 200 MHz. I can observe data being written into the FIFO, but the programmable full flag never asserts. Rather, the programmable empty flag occasionally asserts and then deasserts. I've got the prog. full flag set to 32 and the prog. empty flag set to 2, with the FIFO depth at 64. I've verified that timing constraints are applied, and that there aren't any timing errors. I believe that I'm resetting the FIFO after configuration, for at least three write clock periods. I'm at wit's end here - heck I've just about given up and am writing a FIFO from scratch to work around this. Has anybody seen anything like this before? I sure could use some help . . .
10-01-2008 04:45 AM
I've been working on 9.2i and used programmable full flags as well. They worked fine so far. Have you tested to write only, but never read from the FIFO? If so, then scratch the rest of my posting. Otherwise, at what effective speed are you writing to and reading from the FIFO? Maybe the reason for the flag to never be asserted is that the conditions to assert the flag is never met. In example, if both sides access the FIFO at full speed in regard to their clock domain (writing with every 8ns and reading every 5ns), the FIFO should never become full nor anywhere close to half-full.
10-01-2008 08:16 AM
Thanks for your response! In my design, writes occur infrequently (the FIFO data comes from a decimator). Reads won't occur until the FIFO programmable full flag asserts. Since it doesn't, I don't ever read data from the FIFO. Regards,
10-01-2008 11:55 PM
that sounds odd indeed. That and that you see the empty flag to toggle once in a while. Can you post your FIFO instanciation?