05-20-2018 05:31 AM
I am running asynchronous FIFO simulation and seeing write acknowledge port strange behavioral.
After enabling wr_en signal, the wr_ack goes high after very long time. Please see the screen shot attached:
In Xilinx FIFO IP documentation – PG057, in the waveofrms it is shown that wr_ack goes high after 1 clock cycle after enabling wr_en.
Can someone please explain why in my case wr_ack goes high so late after enabling wr_en signal?
05-20-2018 06:24 AM
because your full ?
You can't write to a full fifo, so till you read, there is no write to ack ?
and as write and read are on different clocks , theres a synchronisation mechanism between the two clocks,
which gives the delay of a few clocks.
05-20-2018 06:07 PM
Hmm strange, from the waveform it can be seen that full is high during reset also. In other words when rst is high full is also high, it is strange.
With regards to delay, as far as i know wr_ack does not have any sync device so it does not contain any delay, but empty,full have