UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer p.hayk
Observer
663 Views
Registered: ‎11-21-2013

FIFO wr_ack signal goes high too late after enabling wr_en.

Dear Forum,

I am running asynchronous FIFO simulation and seeing write acknowledge port strange behavioral.
After enabling wr_en signal, the wr_ack goes high after very long time. Please see the screen shot attached:

 

Screenshot from 2018-05-20 21-10-33.png

 

In Xilinx FIFO IP documentation – PG057, in the waveofrms it is shown that wr_ack goes high after 1 clock cycle after enabling wr_en.

Can someone please explain why in my case wr_ack goes high so late after enabling wr_en signal?

 

0 Kudos
2 Replies
Highlighted
Scholar drjohnsmith
Scholar
654 Views
Registered: ‎07-09-2009

Re: FIFO wr_ack signal goes high too late after enabling wr_en.

because your full ?

 

You can't write to a full fifo, so till you read, there is no write to ack ?

 

and as write and read are on different clocks , theres a synchronisation mechanism between the two clocks,

    which gives the delay of a few clocks.

 

  

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Tags (1)
0 Kudos
Observer p.hayk
Observer
619 Views
Registered: ‎11-21-2013

Re: FIFO wr_ack signal goes high too late after enabling wr_en.

Hmm strange, from the waveform it can be seen that full is high during reset also. In other words when rst is high full is also high, it is strange.

With regards to delay, as far as i know wr_ack does not have any sync device so it does not contain any delay, but empty,full have

0 Kudos