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hadee
Observer
Observer
571 Views
Registered: ‎08-21-2012

Floating-Point IPcore maximum clock

My Block design has IPcore <-> Floating IPcore <-> DMA <-> Zynq

I use floating ipcore to convert from floating point to fixed precision

 

I can use maximum clock as 200MHz from FCLK0 and it is worked perfectly.

 

When I try to use 220 or 250 MHz, I have got the wrong results. So Can i assume that maximum clock for floating IPcore is 200MHZ?

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5 Replies
baltintop
Voyager
Voyager
563 Views
Registered: ‎06-28-2018

Hi @hadee 

Did the design pass timing when you specified the clock frequency as 220MHz or 250MHz in the constraints? If yes then it shouldn't fail on the hardware.

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hadee
Observer
Observer
445 Views
Registered: ‎08-21-2012

Thank you for answer,

I think you're right. My design failed to meet the timing requirements. 

 

Anyway, when I decrease speed to 100MHz and I still got the timing problem but the IPcore is working.

The problem is here.

clock.png

I have arrays of 4 dimensions as memory block in IPcore.

From the picture, The problem is in the path that connect to ram_reg.  Do you have any idea how to fix it?

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baltintop
Voyager
Voyager
441 Views
Registered: ‎06-28-2018

Hi @hadee 

Can you share the timing report?

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hadee
Observer
Observer
433 Views
Registered: ‎08-21-2012

Yes, here you are.

 

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baltintop
Voyager
Voyager
423 Views
Registered: ‎06-28-2018

Hi @hadee 

Those are some beautiful paths. All you have to do is pipeline your logic a bit in order to decrease the logic levels, which are not that high really, or choose a different implementation strategy.

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