04-06-2020 06:30 AM
My Block design has IPcore <-> Floating IPcore <-> DMA <-> Zynq
I use floating ipcore to convert from floating point to fixed precision
I can use maximum clock as 200MHz from FCLK0 and it is worked perfectly.
When I try to use 220 or 250 MHz, I have got the wrong results. So Can i assume that maximum clock for floating IPcore is 200MHZ?
04-06-2020 06:42 AM
04-13-2020 02:53 AM
Thank you for answer,
I think you're right. My design failed to meet the timing requirements.
Anyway, when I decrease speed to 100MHz and I still got the timing problem but the IPcore is working.
The problem is here.
I have arrays of 4 dimensions as memory block in IPcore.
From the picture, The problem is in the path that connect to ram_reg. Do you have any idea how to fix it?
04-13-2020 03:39 AM
Those are some beautiful paths. All you have to do is pipeline your logic a bit in order to decrease the logic levels, which are not that high really, or choose a different implementation strategy.