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Visitor
Visitor
703 Views
Registered: ‎07-25-2020

How to do a behavior simulation of PLL generated from clocking wizard?

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Hi, I'm a new one using Vivado, and  recently, I'm trying to learn how to achieve behaviour simulation of PLL generated from clocking wizard(20MHz to 240MHz). But I encountered some questions, I need your help.

The source document is shown as below:

module NOT_gate(
input in,
//input reset,
output out
    );
//    assign out = ~in;
clk_wiz_0 pll(.clk_out1(out), .clk_in1(in));
endmodule
The testbench:
module simulation(

    );
    reg clk = 0;
    always #50 clk = ~clk;
    
    wire out;
//    wire reset = 0;
    NOT_gate NOT(.in(clk), .out(out));
endmodule
And the simulation results:
 
T4FMD54D[]_CJ9P~JZ0)@9T.png
 
 

Thanks for helping me.

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Xilinx Employee
Xilinx Employee
692 Views
Registered: ‎06-02-2017

Hi @Leaner ,

To generate a 20MHz clock stimulus, it should be:

always #25 clk = ~clk;

And before the your module "simulation" definition, you have to specify the timescale:

`timescale 1ns / 1ps

Then, run the simulation longer than 20us to wait for the generated clock being locked.

View solution in original post

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Xilinx Employee
Xilinx Employee
693 Views
Registered: ‎06-02-2017

Hi @Leaner ,

To generate a 20MHz clock stimulus, it should be:

always #25 clk = ~clk;

And before the your module "simulation" definition, you have to specify the timescale:

`timescale 1ns / 1ps

Then, run the simulation longer than 20us to wait for the generated clock being locked.

View solution in original post

Highlighted
Visitor
Visitor
682 Views
Registered: ‎07-25-2020

Thanks for your reply, and now, I can get right results!

But, I have a new questions about the results, the simulation result is as follows:

8GE@3%86LXYO6ALU0{ZZIQL.png

 The output of PLL is ok after about 3.3us. How to understand the results between 0 ~ 3us?

Thanks for helping me.

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Xilinx Employee
Xilinx Employee
657 Views
Registered: ‎06-02-2017

Hi @Leaner 

That's how the MMCM/PLL works. It must cost some time to achieved phase alignment within a predefined window and frequency matching within a predefined PPM range.

LOCKED will be asserted after the output clock gets stable if it's enabled in the IP.

Highlighted
Visitor
Visitor
650 Views
Registered: ‎07-25-2020

Thank you very much, I get it.

Do you know which user guide documents cover the principle of PLL(including explanation of the reset, locked, etc)?

Thanks for your reply.

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Xilinx Employee
Xilinx Employee
644 Views
Registered: ‎06-02-2017

Hi @Leaner 

UG472 for 7-ser devices, UG572 for US/US+ devices.

PG065 for the Clocking Wizard IP.

 

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Visitor
Visitor
642 Views
Registered: ‎07-25-2020

Thanks!

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Newbie
Newbie
610 Views
Registered: ‎07-26-2020


Didnt expect to get a direct answer so soon! Thank you!

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Visitor
Visitor
537 Views
Registered: ‎07-25-2020

Do you meet the same problem?

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