How to make Vivado infer a Master xilinx.com:interface:bram_rtl:1.0 interface on a RTL/Verilog Module?
I'm using Vivado 2018.3 in this design. I'm trying to make Vivado infer a MASTER xilinx.com:interface:bram_rtl:1.0 on my Verilog module. The idea is to connect my module to the BRAM_PORTB of the Block Memory Generator below:
I've looked at the "Language Template => Verilog => IP Integrator HDL => Advanced Interfaces => Block RAM interface", however it only shows a slave example: