How to make Vivado infer a Master xilinx.com:inter...

brasilino · ‎11-12-2020

Hello!

I'm using Vivado 2018.3 in this design. I'm trying to make Vivado infer a MASTER xilinx.com:interface:bram_rtl:1.0 on my Verilog module. The idea is to connect my module to the BRAM_PORTB of the Block Memory Generator below:

I've looked at the "Language Template => Verilog => IP Integrator HDL => Advanced Interfaces => Block RAM interface", however it only shows a slave example:

I tried many things. The last try was:

module bram_read (
        input wire                  ACLK,
        input wire                  ARESETN,

        input  wire					START,
        output wire					DONE,
        output wire					VALID,
        output wire [ 31 : 0 ]		DATA,

        (* X_INTERFACE_PARAMETER = "MODE Master, MASTER_TYPE BRAM_CTRL, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1" *)
        (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 rstb RST" *)
        output wire					rstb,
        (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 clkb CLK" *)
        output wire					clkb,
        (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 addrb ADDR" *)
        output wire [ 31 : 0 ]		addrb,
        (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 web WE" *)
        output wire [ 3 : 0 ]		web,
        (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 enb EN" *)
        output wire					enb,
        //(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 regceb REGCE" *)
        //output wire					regceb,
        (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 dinb DIN" *)
        output wire [ 31 : 0 ]		dinb,
        (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 doutb DOUT" *)
        input  wire	[ 31 : 0 ]		doutb

        );

But Vivado keeps inferring all ports as separate interfaces.

So, any help on how make Vivado understand those ports as a bram_rtl interface, just like "BRAM_PORTA" on "AXI BRAM Controller" IP ?

Thanks!

Brasilino

How to make Vivado infer a Master xilinx.com:interface:bram_rtl:1.0 interface on a RTL/Verilog Module?