10-25-2009 08:45 PM
I implemented a block RAM fifo via CORE Generator. I received a warning when I was simulating the design.
# ** Warning: (vsim-3473) Component instance "i_read_path_fifo_a : read_path_fifo_a" is not bound.
Althrough the simulation continues, the output signals involved with the fifo outputs are undetemined.
How to simulate a design with a ip core?
By the way, I design in ISE10.1 and simulate in MordelSim 6.2b.
Thank your very much for your kind attention!
10-26-2009 12:56 AM
coregen outputs a set of files, which contains (amongst others) a netlist file for synthesis and a simulation wrapper for the coregen-library element.
I don't know wether ISE cares about this automatically when you work with the XCO Files, or if you still have to add the wrapper manually.
Another pitfall is that the simulation wrapper is generated in the wrong HDL. Check the output files and your coregen preferences.
Once you have the right files with the right names used in your simulation project it all works fine.
Have a nice simulation
10-26-2009 08:16 PM
I find the problem today.
I didn't compile the XilinxLib after I installed IP core updater.
So Modelsim can not find the component FifoGenerator4.4.
After I renewed the XilinxLib, the simulation went on smoothly.
Still, thank you very much for your help!
School of Astronautics,
Harbin Institute of Technology.