I downloaded a project from https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9009/zc706 for Zync3-Eval-Board. This project was written in verilog and I wanted in VHDL. So, I changed the project language to VHDL, re-generated the HDL wrapper and re-wrote the top system file(according to original verilog system file and incorporating newly generated system wrapper file) in VHDL language. When I try to synthesize my project then it gives following error that [IP_Flow 19-182] Failed to load BOM file '/projects/adrv9009/zc706/project_try_vhdl/project_try_vhdl.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xml'. I am using vivado 2019.1 in ubuntuMate environment. I am attaching my vivado.log for further help in your analysis.
I have double checked my localization, specifier, decimal separator format, etc. and they are on en_US.UTF-8.
I have also reset the project through tcl command, reset the BD output products and then tried to re-synthesize my project but no luck.
Note: The original project written in verilog was successfully synthesized in same vivado without any issue.