IP JESD204B lanes mismatch tolerance

[ba_moduleus]

Hi,

I would like to use the IP JESD204B, and I would like to know the mismatch tolerance on the PCB allowed between lanes in a same GTY (VUP) which can be compensated by the ILA by the ILA (Initial Lane Alignment )?

Thanks

[rkhatri · Accepted solution]

Hi @ba_moduleus ,

The JESD204B receiver core has been verified to function with a lane to lane skew of up to 8 octets.

[ba_moduleus]

Hi @rkhatri ,

Thanks for your answer.