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Observer
Observer
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Registered: ‎07-23-2009

Input Clocks MUX for Ulrascale FPGA

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Hi,

I need a MUX to select between two input clocks in Ultrascale+ MPSOC FPGA and I am getting the sub-optimal placement error no matter what primitive I use for the clock mux such as BUFGMUX or BUFGMUX_CTRL.
Both pins reside in the same FPGA bank and clock region.
The only way that works is to use a regular RTL MUX as one would do with a regular signal. Then the project builds and no complaints and I can see in timing analysis that the tool is evaluating these as a clocks (not regular signals). So, wondering if this is ok to do?

Here my code snippet, for the case where it fails:

BUFGMUX_CTRL_i0 : BUFGMUX_CTRL
     port map (
        O => MuxVidClk,   -- 1-bit output: Clock output
        I0 => EIA_49_09M_in, -- 1-bit input: Clock input (S=0)
        I1 => CCIR_95M_in, -- 1-bit input: Clock input (S=1)
        S => vidClk_sel    -- 1-bit input: Clock select
     );

My XDC (xczu3eg-sfvc784-2-i):

set_property IOSTANDARD LVCMOS18 [get_ports {EIA_49_09M_in}]
set_property PACKAGE_PIN E12 [get_ports {EIA_49_09M_in}]

set_property IOSTANDARD LVCMOS18 [get_ports {CCIR_95M_in}]
set_property PACKAGE_PIN E10 [get_ports {CCIR_95M_in}]

create_clock -period 20.370 -name EIA_49p09MHz_in [get_ports EIA_49_09M_in]
create_clock -period 16.949 -name CCIR_95MHz_in [get_ports CCIR_95M_in]

# Metualy exclusive clocks
set_clock_groups -logically_exclusive -group CCIR_95MHz_in -group EIA_49p09MHz_in

Thank you

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129 Views
Registered: ‎01-22-2015

@lyrfpga06 

Your clocks are entering the XCZU3EG on GC pins in HD bank 84.  As described on page 10 of UG572(v1.10), the HD-GC pins can only directly drive BUFGCEs.  -and sometimes setting CLOCK_DEDICATED_ROUTE = FALSE is necessary.

So, for your clocks, route each through a BUFGCE before sending them to the BUFGMUX.  Then, as suggested by the Vivado errors you are receiving, add constraints like the following to your .xdc constraints file.

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets EIA_49_09M_in_IBUF_inst/O]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CCIR_95M_in_IBUF_inst/O]


Cheers,
Mark

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130 Views
Registered: ‎01-22-2015

@lyrfpga06 

Your clocks are entering the XCZU3EG on GC pins in HD bank 84.  As described on page 10 of UG572(v1.10), the HD-GC pins can only directly drive BUFGCEs.  -and sometimes setting CLOCK_DEDICATED_ROUTE = FALSE is necessary.

So, for your clocks, route each through a BUFGCE before sending them to the BUFGMUX.  Then, as suggested by the Vivado errors you are receiving, add constraints like the following to your .xdc constraints file.

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets EIA_49_09M_in_IBUF_inst/O]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CCIR_95M_in_IBUF_inst/O]


Cheers,
Mark

View solution in original post