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wojtech
Visitor
Visitor
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Registered: ‎12-28-2016

JESD204B on ZCU102

I am trying to get JESD204B to work on a ZCU102.

I am using Vivado 2016.4 and a design that is closely based on the KCU105 design made for the Ultrascale JESD204B Hardware Demo in the JESD lounge. 

 

My problem is that I cannot even achieve sync. It might be something to do with the fact that ZCU102 uses GTHE4 instead of GTHE3 like the KCU105. For example, the driver files shipped with the hardware demo contain a folder

uhwd_2016_3_v1_0\sw_src\XilinxProcessorIPLib\drivers\jesd204_phy_v3_2\src\lrt\release\GTHE3

and

uhwd_2016_3_v1_0\sw_src\XilinxProcessorIPLib\drivers\jesd204_phy_v3_2\src\lrt\release\GTXE2 

but not GTHE4.

 

The folder is timestamped as 2016-11-23. Should this driver even support ZCU102?

Can you point me to a current driver?

 

 

 

 

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5 Replies
wojtech
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3,428 Views
Registered: ‎12-28-2016

I have gotten in touch with my Xilinx contact and would like to share his reply for others here:

 

He said that simply porting my software may be somewhat fruitless.

The speed switching tables are for the GTHE3 transceivers on the KCU105 and the ZCU102 has GTHE4 transceivers.

These transceivers share a very similar architecture, but are on a different process node so the reality is that they are quite different.

He said I  should be able to get the rest of it to work by configuring the JESD portion with a static (fixed linerate and refclk) configuration. Then in time I can merge the changes Xilinx makes for future USHW / driver versions.

However I am now not sure if this means that I can get JESD to work at all or if I have to wait for a new release by Xilinx.

 

On a side note, I had asked why Xilinx used location constraints to attach the JESD lanes to pins. He told me that in earlier versions of Vivado it was not possible to put pin constraints on transceivers so as often, the answer is "legacy".

 

If someone has any experience with getting JESD204B to work on ZCU102, I would still greatly appreciate any pointers.

 

 

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iceyefpga
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Registered: ‎09-11-2013

Hi Wojtech,

I am also trying to get my ZCU102 running with a JESD204B converter. I am using DAC37J82EVM module from TI. Did you manage to get your ADC running?

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dancurry
Adventurer
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2,610 Views
Registered: ‎10-26-2017

I am working on a similar project with JESD204b on the ZCU102. I was able to obtain a successful SYNC signal, and have probed inside the core to find valid RX data and corresponding rx_valid signals, however the core's top-level rx_tvalid and rx_tdata pins remain low. Has anyone had success implementing this for ZCU102?

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namnb@interland.vn
Contributor
Contributor
2,517 Views
Registered: ‎07-07-2014

Dear wojtech!

Have you fixed this? I am facing the same your problem.

I am working on ZC102(GTHE4) with ADC AD9680.

I  am neither rx_sync or rx_tvalid ever turn high and JESD204 is always on reset state.

I tried to configure with XC706 for GTX transceivers and the result is OK but  with  ZC102(GTHE4) is not.

If you fixed it, please help me.

Many Thanks!

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Spencer
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Registered: ‎09-13-2020

Hi Iceyefage

Did your design work? Can you share your design with me? Thanks!

 

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