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mwinston
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Registered: ‎02-28-2013

Logicore 11.0 Binary Counter Latency Settings

What do these settings control and how/when would you use them?

 

I'm asking b/c I'm having some trouble with a design where I load the counter on the same clock cycle that increment it. Specifically, the load signal goes high once cycle before the input clock goes high.    After the load, the values on the output of my 32 bit counter are weird.  For example, I load 2271560481 and I read out 2267021605.  Simulation works fine, but implementation doesn't.  

 

Thanks for the help.

Mark

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bassman59
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Registered: ‎02-25-2008


@mwinston wrote:

What do these settings control and how/when would you use them?

 

I'm asking b/c I'm having some trouble with a design where I load the counter on the same clock cycle that increment it. Specifically, the load signal goes high once cycle before the input clock goes high.    After the load, the values on the output of my 32 bit counter are weird.  For example, I load 2271560481 and I read out 2267021605.  Simulation works fine, but implementation doesn't.  

 

Thanks for the help.

Mark


I haven't looked at this particular core, but why even bother using it?

A binary counter is a half-dozen lines of VHDL.

----------------------------Yes, I do this for a living.
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mwinston
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Registered: ‎02-28-2013

Thanks.  You have a good point.  Honestly, I'm new to both FPGA's and vhdl and on a short timeline to get this project done.  So I figured the safest bet was to go with the available core.    If you have an example of a counter with load functionality I could use as a starting point, that would be much appreciated.  I'll do some searching on the net for some examples also.  

Thanks for you reply.

Mark

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bassman59
Historian
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Registered: ‎02-25-2008


@mwinston wrote:

Thanks.  You have a good point.  Honestly, I'm new to both FPGA's and vhdl and on a short timeline to get this project done.  So I figured the safest bet was to go with the available core.    If you have an example of a counter with load functionality I could use as a starting point, that would be much appreciated.  I'll do some searching on the net for some examples also.  

Thanks for you reply.

Mark


One of the first things you learn in VHDL is how to implement a counter.

 

In the architecture's declarative section, put something like: 

 

constant COUNTMAX : natural := 1234;

signal counter    : natural range 0 to COUNTMAX - 1;

signal loaden     : std_logic := '0';

signal counten    : std_logic := '0';

 

and in the architecture's body, put something like:

 

    mycounter : process (clk) is

    begin

        clockedge : if rising_edge(clk) then

            loadorcount : if loaden = '1' then

                counter <= loadval;

            elsif counten = '1' then

                counter <= (counter + 1) mod COUNTMAX;

            end if loadorcount;

        end if clockedge;

    end process mycounter;

 

Details of how the control signals are generated is an exercise left to the reader.

----------------------------Yes, I do this for a living.
balkris
Xilinx Employee
Xilinx Employee
9,498 Views
Registered: ‎08-01-2008

I think you need to check generated report. It seems something is optimize which result in data corruption.
Thanks and Regards
Balkrishan
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