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Anonymous
Not applicable
13,642 Views

Lower DDR Clock

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Hi,

 

I'm using MPMC as DDR controller and it's working fine at 100MHz on XUP-VirtexIIPro. When I lower the clock to 50mhz, the memory starts malfunctioning, like returning wrong data sometimes. Is there a config I should be doing that I'm missing? I'm guessing it's the refresh command rate, whihc is lower now with the decreased clock rate, but don't quite know how to set it!

 

Thanks, 

Kaveh 

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barriet
Xilinx Employee
Xilinx Employee
20,487 Views
Registered: ‎08-13-2007

This is not unexpected.

Note that DDR SDRAM is not designed to run over the entire range from DC to its maximum frequency.

 

As an example, look at this datasheet:

http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf

You'll notice on page 50, that you are not allowed to run this memory below 75MHz.

 

There is also this note on page 33:

/*

The current Micron part operates below 83 MHz (slowest specified JEDEC operating
frequency). As such, future die may not reflect this option.

*/

 

I have seen users operate the memory below its minimum frequency (or try to). Sometimes it works - and even then sometime only until the next rev of the memory.

 

Just a general note to indicate that the considerations here aren't limited to just the FPGA and its associated performance.

 

bt

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barriet
Xilinx Employee
Xilinx Employee
20,488 Views
Registered: ‎08-13-2007

This is not unexpected.

Note that DDR SDRAM is not designed to run over the entire range from DC to its maximum frequency.

 

As an example, look at this datasheet:

http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf

You'll notice on page 50, that you are not allowed to run this memory below 75MHz.

 

There is also this note on page 33:

/*

The current Micron part operates below 83 MHz (slowest specified JEDEC operating
frequency). As such, future die may not reflect this option.

*/

 

I have seen users operate the memory below its minimum frequency (or try to). Sometimes it works - and even then sometime only until the next rev of the memory.

 

Just a general note to indicate that the considerations here aren't limited to just the FPGA and its associated performance.

 

bt

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Anonymous
Not applicable
13,605 Views

Thanks for the details. I guess I have to improve my design so it runs at 100MHZ then :)

 

Cheers, 

Kaveh 

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