as in AXI Addressing it is mentioned that EX , if payload load is 16 then log2(16)-3=1 , these one bit will be ignored and masked then, why in bit width calculation we have log2(PAYLOAD_WIDTH) – 3 , as this term is telling which bits are ignored and masked we can ignore this right.
then C_S_AXI_ADDR_WIDTH = log2(RANKS) + ROW_WIDTH +COL_WIDTH + BANK_WIDTH
this ranks ,row_width, col_width, bank_width we be able to give the address width right
Not quite. The C_AXI_ADDR_WIDTH is the width required to access an octet (8-bits) of information. It should be the log, based 2, of the size of your SDRAM--independent of any row, column, or bank address widths. That mapping you'll have to do yourself.