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harshalrode
Contributor
Contributor
10,345 Views
Registered: ‎10-01-2009

Need help in using IP cores in ISE

Hi

 

I want to use 2 IPs in a project FIFO and Memory interface. I am able to generate core for FIFO but how to generate both of them and use them together ?

 

are there any documents for coregen module use?

 

Thank you

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luisb
Xilinx Employee
Xilinx Employee
10,051 Views
Registered: ‎04-06-2010

You're going to have to have a top level file that instantiates both modules. If you want to use the FIFO within the MIG core then I recommend adding all the rtl to the design.
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