I have a program in VHDL language,and I can synthesize it in ISE without any error,and my program composed from some VHDL module and one FIFO from IP(coregen).
and i know we can't simulate the IP(core gen).
I can simulate each module separately and see the result but when i try simulate whole the program by ISE simulator or Model Sim XE ,while processing and runing to simulate suddenly jump out and do nothing without any error or warning as same as i've never ran it .(I don't know why?)
I hvae done it for different boards and it didn't work, and install my ISE software again and again but it didn't work.
please help to find solution beacause i really need to see the result.