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raff5184
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Registered: ‎02-21-2019

Rading BRAM from custom IP (Verilog)

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Hi,
I'm new to this topic. Basically I have a Verilog module that receives 16-bits packets. I want to create a custom IP module in Vivado with my Verilog code that get the data from a BRAM.

I have a couple of possibilities, I can create an AXI (AXI-Lite) interface to read from the BRAM, but then I don't know how to pass the data from the AXI interfce to my core.

Or I can interface directly with the BRAM, but I'm not very familiar with how this is done. I think I should create a FSM that reads from the BRAM and so I have the data that I can feed to my core.

I need a very simple solution that I can implement relatively quickly.

Any example or simple tutorial (in Verilog)?

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dpaul24
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Registered: ‎08-07-2014

@raff5184 

I need a very simple solution that I can implement relatively quickly.

1. It heavily depends on the core which interfaces with your BRAM. If you core has a an AXI i/f, then it is a good idea to generate Xilinx BRAM with AXI i/f (a few clicks with the FIFO Gen GUI will achieve that). The logic insid eyour core should generate the AXI transactions such that data is read from the BRAM.

2. If you core has a custom i/f, then generate the BRAM with non-AXI/native i/f. In this case also have a logic in the core (or a wrapper over the core), probably a SM that will generate the read strobes for the BRAM.

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dgisselq
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Registered: ‎05-21-2015

How about this example?  It creates a local block RAM, and then handles AXI-lite requests to read and write from it.  The block RAM is inferred, though, so it doesn't use any explicit Xilinx block RAM IP primitives.  Indeed, I typically infer all of my block RAMs from Verilog.

Ideally, I'd want to recommend using the Vivado generated AXI-lite code and just adding a block RAM to it.  However I haven't heard if they've fixed the bugs in that code (yet) and I just replied to a forum post today where someone was still struggling with the bugs within it.

Dan

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dpaul24
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Registered: ‎08-07-2014

@raff5184 

I need a very simple solution that I can implement relatively quickly.

1. It heavily depends on the core which interfaces with your BRAM. If you core has a an AXI i/f, then it is a good idea to generate Xilinx BRAM with AXI i/f (a few clicks with the FIFO Gen GUI will achieve that). The logic insid eyour core should generate the AXI transactions such that data is read from the BRAM.

2. If you core has a custom i/f, then generate the BRAM with non-AXI/native i/f. In this case also have a logic in the core (or a wrapper over the core), probably a SM that will generate the read strobes for the BRAM.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.

View solution in original post

raff5184
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Registered: ‎02-21-2019

@dpaul24   I used the second approach and it worked. I basically looked at the BRAM IP block and the input and output signals that its interface has and created my corresponding signals to read from it. 

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