I need to implement the RX & TX FIFOs, which should hold the Ethernet packets (queue of packets) and be read by Zynq/uBlaze.
The FIFOs should be able to hold up to 10 Ethernet packets of ~1.5KB each one. The Ethernet is 10GB one.
What FIFOs are most suitable for this purpose (AXI Streaming FIFOs, etc)? Should DMA be involved in the reading the FIFOs?
Could the Zynq MAC DMA be involved to read FIFOs, which are implemented in the Programmable portion of FPGA? How?
Could the uBlaze be fast enough in order to read the FIFOs?