UltraRAM Asynchronous Read Behavior

[chsdkj]

UG573 (v1.9) indicates with regard to UltraRAM dual-port operations (p.113) that "The operation of port A is always executed first followed by the operation of port B within the same clock cycle."

Clarification is needed regarding whether this implies, when the two ports are configured to produce read output data asynchronously, that port A read data will be available before port B read data, and therefore in the case of needing only one output port that it is port A that should usually be used due to its shorter read-output-data delay time.

[jdehaven]

Running a test case through a timing simulation should answer this. However, if would be nice if this was clarified in the docs.

[necare81]

The docs are very clear that asynchronous read is not supported for UltraRAMs (or Block RAMs for that matter).   Only the reset set can be configured to be asynchronous for UltraRAMs.

In Sync mode, if you stop the clocks you can change the address and the reset all you like but it will not change the outputs.

In Async mode, if you stop the clocks you can change the address but the outputs will never change, if you assert reset the outputs will quickly go to 0.

The only memory that supports asynchronous operation is the Distributed RAM (aka LUTRAMs).

Block RAMs only have synchronous resets, the only asynchronous input is the sleep.

[chsdkj]

necare81,

Sorry for not having been clearer in my original post.  By "...the two ports...configured to produce read output data asynchronously..." was meant "...the two ports...configured to produce read output data without output registers being present/enabled...".

The question stands regarding whether port A read data will be available before port B read data, i.e., following the rising edge of the input clock.