09-02-2009 07:00 AM
I want to do something which is very simple, I have designed a small SoC complete with a custom 32bit processor which I am implementing in a spartan 3. I am using a coregen generated dual port block ram as an instruction/data memory, and I'd like to be able to make software changes without re-implementing the entire design right from synthesis through bitgen. So my question is can this be done?
Right now what I am doing is manually updating the .coe txt files and then opening up coregen and reconfiguring the ram with the newly updated .coe file, then re-running bitgen all over again each time I make a software change. I am using a gcc compiler to compile the C++ code and it basically spits out the binary code I need to put into the ram, I'm an literally just cutting and pasting that information into the .coe file and following the process I described above. THERE HAS GOT TO BE AN EASIER WAY, SOMEONE HELP ME ON THIS PLEASE!!!!:smileymad:
09-02-2009 08:04 AM
Yes there is an easier way. It's called data2mem
09-02-2009 08:49 AM
09-02-2009 09:06 PM
This thread has a lot of useful links to data2mem information
09-03-2009 06:20 AM
Forgive my frustration, but is this some sort of secret amongst xilinx employees which you guys do not want to let the customer in on. What I am asking is very simple to understand, why I keep getting mountains of information from you guys is beyond me. Does anyone at this company know how this can be done? I need a simple direct answer as to how to get this too work, this is an FPGA the point of this tool is prototyping by and large, how are customers supposed to prototype processor systems without a convenient way of updating instruction cache? Is xilinx saying that the best it can do is advise the customer to re-implement the entire hardware design every time they make a change to software, or is there some secret method only xilinx employees are allow to use?
I need someone to explain to me how this can be done and not point me to a book, I've looked at the book its not clear even there how to build the bmm files, I've tried and get errors that don't make sense, I've read the answers data base responses on this issue with no success, I need someone who knows exactly how to get this done, to show me the way step by step. I'm sorry but after designing an entire SoC from scratch and choosing xilinx fpgas over their competitors the least you guys can do is help me out on a method to conveniently updating my cache without waiting 45mins to re-implement every single time. I need help people someone please!
09-06-2009 08:01 PM
Cool down ... I understand your frustration. Let me try to help you.
Correct me If i am wrong.
You are using a Processor and you need to load the Instruction Memory, without going through the whole implementation process.
What you have is the .elf file
Can you tell me the size( width and depth ) of the block ram you are using and the address space of the processor?
09-08-2009 06:25 AM
09-08-2009 11:39 AM
The ram I am using is a core generated dual port block ram it is 32 bits wide and has 13 address bits. Let me know if you need any further information.
I still don't understand why you resist learning about how to use Data2Mem. It does EXACTLY what you wish to do!
09-08-2009 12:45 PM
09-08-2009 01:16 PM
Have you tried creating the BMM manually? You can use Data2MEM to perform a syntax on your .bmm before replacing the Block RAMs with the new data. If this still fails there might be a problem with your ELF file.
If you are still having problems please open a webcase with World Technical Support at http://www.xilinx.com/support/clearexpress/websupport.htm.