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awoz92gmu
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Registered: ‎11-26-2018

VHDL example of cascading FIFO18E2 primitives serially or in parallel?

Hi I'm trying to cascade Ultrascale FIFO18E2 and FIFO36E2 primitives together to make larger FIFOs in depth and width. I was wondering if Xilinx or anyone else has VHDL example code of how to do this? I've been referencing ug974 and ug573.

Any direction is appreciated. 

 

Alex

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drjohnsmith
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Registered: ‎07-09-2009

There is an easy way,

 

If you use the fifo generator IP in Vivado,

you "just" define the fifo type ( common clock, block ram, dist ram etc ) and the size,

   and the tool wraps up together the fifos you need, and does all the layout tricks for you

 

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awoz92gmu
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Registered: ‎11-26-2018

I have considered using the FIFO generator IP, but doe the IP generator only utilize FIFO primitives? Because that is what I'm trying to acomplish. 

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drjohnsmith
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Registered: ‎07-09-2009

you select what you want the fifo made out of , one option is the built in fifos',

Out of interest, why do you want the built in fifos only ?

 

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awoz92gmu
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Registered: ‎11-26-2018

Okay then I will give the FIFO generator a shot. 

I have a near full FPGA, and I want to only use built in FIFOs to reduce/free-up other resources. I'm trying to optimize several FIFO components in my design. 

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drjohnsmith
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Registered: ‎07-09-2009

sounds a good reason,

   You have the block rams free to do that then ? ( the in built fifos are in the Block rams )

Its a pain when FPGAs become full.

   I have a constant "discusion" with my clients who want to sav eX and use a smaller FPGA .

     I normaly end up going back a year later and designing in a bigger FPGA !

 

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awoz92gmu
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Registered: ‎11-26-2018

Yes I believe I have enought BRAM free to do this. 

And yes it would be great if I could just use a larger FPGA but unfortunitely it's not an option...

Thanks for the tips.  

awoz92gmu
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Registered: ‎11-26-2018

I had a question about the FIFO generator IP. 

I'm aware that the IP generator will cascade the the appropriate number of FIFO primitives together based on the requested FIFO depth/width.

But is there a way to generate a FIFO IP then request different depths and widths after it's been generated? And will it still cascade the right amount of FIFOs?

Or does it only cascade the right number of FIFOs at generation and after that it is fixed and you cannot change the FIFO depth or data width?

It seems like you can't, and which is why I think I'll have to use the FIFO primitives anyways so I can have configurable FIFOs. 

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drjohnsmith
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Registered: ‎07-09-2009

Nope,

an IP does not have generics to vary the size,

( not least of which , Xilixn use Verilog, which has poor generic support )

 

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