01-16-2018 08:39 PM - edited 01-16-2018 08:40 PM
I want to used vivado IP Catalog to generator block ram IP, and configure initial value.
But in FPGA verify, the initial value is 02FFFFFE, this value is not my configure.
How to resolve this issue?
In simulation waveform:
Memory_initialization_radix = 16; Memory_initialization_vector = EAFFFFFE 00000000;
01-16-2018 08:49 PM
01-16-2018 11:55 PM
What is this FPGA verify tool?
01-17-2018 12:42 AM
01-17-2018 03:08 AM
This looks like synopsys tool issue to me as simulation shows proper data. You may have to check with Synopsys support team.
01-18-2018 05:29 AM
Usually when you generate a BRAM IP core that has initial values, you pass a .coe file into the tool (or specify values in the wizard), and the tool generates a .mif file that contains the binary data for each address. The .mif data is what really gets loaded into the memory. Check that the data in the .mif file is correct (it's human readable in a text editor). I had a case several years ago in which Vivado messed up the translation from .coe to .mif, and loaded the wrong data into the BRAM.
01-21-2018 06:35 PM
I check COE and MIF file again, there initial value is the same, but real verify is not there value.
Memory_initialization_radix = 16; Memory_initialization_vector = EAFFFFFE, 00000000;
01-23-2018 01:09 AM - edited 01-23-2018 01:40 AM
Where can I find out the generated .mif file ? In my case, I use the language template of Vivado to infer BRAM with INIT_FILE which I create a .coe. However, in field testing, the default value check doesn't match the .coe file as you did. Thus, I saw your thread and would like to check the generated .mif file first in my case. Thanks
N.B. I use Vivado 2017.2 and in synthesis log runme.log under synth_1 , it does read the .coe file successfully.
01-31-2018 04:30 AM
The .mif file gets generated by the IP Generator; you pass in the .coe file and IP Generator creates the .mif and initializes the BRAM IP core with it. In those cases, the .mif shows up in /project directory/synth/*.ip_user_files/mem_init_files/.
When inferring BRAM from VHDL or Verilog, I usually initialize it with a .mif file that I've previously created by making a similar core in IP Generator. I've never tried initializing inferred BRAM with a .coe file. I doubt Vivado creates a .mif if you let it infer the BRAM.
Does your inferred BRAM simulate correctly, so you know your initialization function is working?
Is your ".coe" file purely binary or hexadecimal? Xilinx coe file syntax includes a header with strings for memory_initialization_radix and memory_initialization_vector. I believe the initialization file expected by inferred BRAM must contain only binary or hexadecimal data, without those strings.
If that's the problem, you probably need to make a .mif file instead of a .coe file.