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rmatsick3
Newbie
Newbie
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Registered: ‎03-31-2021

Vivado 2020.2 Aurora 8b/10b DRP being instantiated after not being selected in IP

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I am using an Aurora 8b/10b core in duplex mode.  I unchecked the 'GT DRP Interface' box because I do not want to use this.  I validated my design within the IP Integrator with no errors or warnings.  I then synthesized the design and I get 27 [Synth 8-4442] Blackbox module critical warnings related to the DRP connections which were generated.  I read some posts related to the DRP interface for this core and tied the drpclk_in low thinking this would eliminate this interface but the problem remains.  Seems like a bug with the IP. I don't like seeing critical warnings in my designs so I am not going to ignore this.  What is the workaround for this?

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rmatsick3
Newbie
Newbie
247 Views
Registered: ‎03-31-2021

Interestingly enough, I was able to "trick" the IP by selecting DRP, generating the output products, and then deselecting DRP, saving and then doing another implementation run.  Very intermittent though as I have copied the project and tried this again and it did not work.  I finally selected DRP, reset the output products, and implemented the design without any [Synth 8-4442] warnings.

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rkhatri
Moderator
Moderator
270 Views
Registered: ‎01-10-2019

Hi rmatsick3,

As a workaround you can add the DRP port from IP and manually connect them to low.

Thanks,
Rahul Khatri
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rmatsick3
Newbie
Newbie
248 Views
Registered: ‎03-31-2021

Interestingly enough, I was able to "trick" the IP by selecting DRP, generating the output products, and then deselecting DRP, saving and then doing another implementation run.  Very intermittent though as I have copied the project and tried this again and it did not work.  I finally selected DRP, reset the output products, and implemented the design without any [Synth 8-4442] warnings.

View solution in original post

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