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davidnvm
Visitor
Visitor
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Registered: ‎02-27-2019

Where to find input_delay for ultrascale BRAM

Hello, I am looking for the input_delay for BRAM in ultrascale.

I found this in the datasheets:

BRAM_VU.png

I understand the clock-to-out delay.

I assume the clock-frequency is for intern clock-to-clock paths

I do not know where to find in-to-clock delays

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markcurry
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Scholar
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Registered: ‎09-16-2009

Huh, that's interesting.  It appears all internal Setup/Hold times (i.e. to any sequential internal FPGA cell: FF, BRAM, DSP48, etc) are now missing from the various "DC and AC Switching Characteristics" documents.

i.e. DS922 (July 12, 2019) (Kintex UltraScale Plus) -  Does not show any internal Setup/Hold times for internal cells.

But

DS183 (March 13, 2019) (Virtex-7) Does show Setup/Hold times for internal cells.

(I've not checked others, I just happened to have these two open...)

I imagine this was done as the variance across all devices was just to much to boil it all down to a meaningful min/max aggregate number.  One needs to look at the actual generated timing reports for your run.

But having a rule-of-thumb number that one could look at inside a datasheet was often helpful.

Regards,

Mark

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davidnvm
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Registered: ‎02-27-2019

Well of course we can just implement it and see the numbers but those numbers will then depends on so many factors... It would be useful to have those numbers in the datasheet.
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