02-07-2020 12:41 AM
Hello, I am looking for the input_delay for BRAM in ultrascale.
I found this in the datasheets:
I understand the clock-to-out delay.
I assume the clock-frequency is for intern clock-to-clock paths
I do not know where to find in-to-clock delays
02-07-2020 11:21 AM
Huh, that's interesting. It appears all internal Setup/Hold times (i.e. to any sequential internal FPGA cell: FF, BRAM, DSP48, etc) are now missing from the various "DC and AC Switching Characteristics" documents.
i.e. DS922 (July 12, 2019) (Kintex UltraScale Plus) - Does not show any internal Setup/Hold times for internal cells.
DS183 (March 13, 2019) (Virtex-7) Does show Setup/Hold times for internal cells.
(I've not checked others, I just happened to have these two open...)
I imagine this was done as the variance across all devices was just to much to boil it all down to a meaningful min/max aggregate number. One needs to look at the actual generated timing reports for your run.
But having a rule-of-thumb number that one could look at inside a datasheet was often helpful.
02-09-2020 11:19 PM