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Way
Adventurer
Adventurer
239 Views
Registered: ‎10-19-2020

Why Aurora 64b/66b sys_reset_out is having unknown value in Simulation?

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Hi,

I am trying to do simulation on Aurora 64b/66b IP core. I refer to the example design and created my own design with the Aurora IP core. Instead of having the share logic included in example design, I am choosing include share logic in core for my own design. I follow the reset sequence mentioned in the user guide where having the reset_pb asserted first then only assert the pma_init and de-assert reset_pb after pma_init de-asserted. 

However, I noticed that the sys_reset_out is going to unknown value in simulation as shown in the snapshot. The other signal is ok such as gt_pll_lock, tx_out_clk and etc. Wonder if what will be causing the sys_reset_out going into a unknown value?

 

 

sys_reset_out.PNG
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guozhenp
Xilinx Employee
Xilinx Employee
112 Views
Registered: ‎05-01-2013

I think Aurora IP core is source open.

The sys_reset_out is from the logic in the module "aurora_64b66b_*_reset_logic.v". Please check the related signals in simulation waveform. You should be able to find the root cause.

always @ (posedge USER_CLK)
SYSTEM_RESET <= `DLY RESET || !fsm_resetdone_sync || power_down_sync || link_reset_sync;

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guozhenp
Xilinx Employee
Xilinx Employee
113 Views
Registered: ‎05-01-2013

I think Aurora IP core is source open.

The sys_reset_out is from the logic in the module "aurora_64b66b_*_reset_logic.v". Please check the related signals in simulation waveform. You should be able to find the root cause.

always @ (posedge USER_CLK)
SYSTEM_RESET <= `DLY RESET || !fsm_resetdone_sync || power_down_sync || link_reset_sync;

View solution in original post

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Way
Adventurer
Adventurer
84 Views
Registered: ‎10-19-2020

Hi @guozhenp 

Thank for the information. I noticed that the root cause is because some of the related signal is not set in my simulation that causes unknown value 

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