cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
johnforumname
Visitor
Visitor
1,384 Views
Registered: ‎12-05-2016

Wrapping RAMB16BWER for Kintex

I want to port a design from a Spartan 6 to Kintex, I have tried to wrap the RAMB8BWER blocks present to replace them with RAMB18E1 on the Kintex.

However, during place_design I get

"ERROR: [Opt 31-30] ............(RAMB8BWER).......... This blackbox cannot be found in the existing library."

My wrapper entity has been added to project and compiled, so why isn't the placer finding it? Below is my wrapper file:-

 

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

Library UNISIM;
use UNISIM.vcomponents.all;

entity RAMB8BWER is
generic (
    -- DATA_WIDTH_A/DATA_WIDTH_B: 'If RAM_MODE="TDP": 0, 1, 2, 4, 9 or 18; If RAM_MODE="SDP": 36'
    DATA_WIDTH_A        : integer := 0;
    .....................................
    WRITE_MODE_B        : string := "WRITE_FIRST"
);
port (
    -- Port A Data: 16-bit (each) output: Port A data
    DOADO               : out std_logic_vector(15 downto 0);
    ..........................................
    DIPBDIP             : in  std_logic_vector(1 downto 0)
);
end entity RAMB8BWER;

architecture rtl of RAMB8BWER is
begin

-- RAMB18E1: 18K-bit Configurable Synchronous Block RAM
--           Kintex-7
-- Xilinx HDL Language Template, version 2016.2

RAMB18E1_inst : RAMB18E1
generic map (
    -- Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE"
    RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
    ..........................................
    WRITE_MODE_B                               => WRITE_MODE_A
)
port map (
                                                    -- Port A Data: 16-bit (each) output: Port A data
    DOADO                     => DOBDO,             -- 16-bit output: A port data/LSB data
    .........................................
    DIPBDIP                    => DIPADIP            -- 2-bit input: B port parity/MSB parity
);

end architecture rtl;

0 Kudos
5 Replies
pthakare
Moderator
Moderator
1,346 Views
Registered: ‎08-08-2017

Hi @johnforumname

Can you please attach a complete .vhd file to check this at our end ? Which VIVADO version you are using ?, It seems to be 2016.2 from the language template you copied.

You can PM me if you dont want to share the .vhd file publicly

--------------------------------------------------------------------------------------------------------------------------------------------

Reply if you have any queries , Give Kudos and accept as solution'

----------------------------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos
johnforumname
Visitor
Visitor
1,344 Views
Registered: ‎12-05-2016

@pthakare

Vivado 2016.2, I've attached the wrapping code

 

I did initially put the whole thing in my answer but trimmed it for brevity

0 Kudos
johnforumname
Visitor
Visitor
1,312 Views
Registered: ‎12-05-2016

@pthakare

I also tried synthesizing it out of context, but the .dcp is empty, how can I get it to stop it optimizing it away?

I've tried putting dont_touch attributes on literally everything in the file, entity/label/signals

set device       "xc7k325t"
set package      "ffg900"
set speed        "-2"
set part         $device$package$speed
create_project -force Project_1 -part $part

read_vhdl ../hdl/RAMB8BWER_wrapper.vhd

synth_design -top RAMB8BWER -mode out_of_context
write_checkpoint -force RAMB8BWER
close_project

0 Kudos
pthakare
Moderator
Moderator
1,295 Views
Registered: ‎08-08-2017

Hi @johnforumname

I changed the design RAMB8WER_wrapper.vhd file slighlty.  The changes are 

1. Matching the entity name with file name  (RAMB8WER_wrapper)

Capture.PNG

2. Adding 3 extra Signal to avoid the concatenating function in the port mapping . earlier this function warnings in synthesis.

ADDRARDADDR <= "0" & ADDRBRDADDR;
ADDRBWRADDR <= "0" & ADDRAWRADDR;
WEBWE <= "00" & WEAWEL ;

With this changes , I am able to Synthesis the design.

Capture.PNG

 Attached is the modified file.

----------------------------------------------------------------------------------------------------------------------------------------------------------------

Reply if you have any queries , Give Kudos and accept as Solution

-------------------------------------------------------------------------------------------------------------------------------------------------------------

 

 

 

             

      

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
johnforumname
Visitor
Visitor
1,265 Views
Registered: ‎12-05-2016

My intention was to allow .ngc files requiring "RAMB8WER" to use my wrapped version, so changing the name defeats the purpose.

However, this doesn't seem possible so I've decided to try something else.

0 Kudos