cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
812 Views
Registered: ‎06-19-2014

fifo depth for asymmetric port width

Jump to solution

I have a fifo whose

wr_clk = 250 MHz and 128 bits are written every wr clock cycle without any break.

rd_clk = 500 Mhz and 16 bits are coming out of fifo as soon as empty flag goes low. (8 cycles of 500 MHz clock to read 128 bits).

How to calculate fifo depth so it does not get full?

0 Kudos
Reply
1 Solution

Accepted Solutions
Highlighted
Scholar
Scholar
801 Views
Registered: ‎08-01-2012

Impossible.

You are writing data 4x quicker than you can read it.

Write side BW = 32GB/s

read side BW = 8GB/s

Also, wondering how you expect to meet timing at 500 Mhz.

I think your clock speeds or data write rate might be wrong.

View solution in original post

0 Kudos
Reply
3 Replies
Highlighted
Scholar
Scholar
802 Views
Registered: ‎08-01-2012

Impossible.

You are writing data 4x quicker than you can read it.

Write side BW = 32GB/s

read side BW = 8GB/s

Also, wondering how you expect to meet timing at 500 Mhz.

I think your clock speeds or data write rate might be wrong.

View solution in original post

0 Kudos
Reply
Highlighted
Explorer
Explorer
797 Views
Registered: ‎06-19-2014

This is zync ultrascale + chip. Can't it meet timing with 500 mhz design? 

What solution do you suggest for this problem. Should I half the wr data width and use 2 fifos? 

0 Kudos
Reply
Highlighted
Scholar
Scholar
792 Views
Registered: ‎08-01-2012

halving the data width and using two fifos means the bandwidth match, but empty will never go low (and you may lose the occasional Dword based on PPM clock differences).

0 Kudos
Reply