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Observer
Observer
1,147 Views
Registered: ‎05-09-2018

i have some questions about using single port BRAM generator

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i'm using vivado 2016.4 Verilog, 

 

i have implemented a RISC processor and i want to connect this with 2 BRAMs. 

one BRAM is an Instruction Memory and another is Data Memory. (external memory)

 

i tested the top module connect with Inst.Mem and Data.Mem which was made by myself before, and test result is correct.

 

but, module with include same source code  (.v files) and substitute myMemory to IP catalog -> Block Memory Generator, test result is not correct.

 

some output signals delayed 1 or 2 clock period.

 

what is my problem? and how can i correct this? 

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Adventurer
Adventurer
1,296 Views
Registered: ‎05-23-2018

Per default, in block memory generator the output registers are active, which cause an additional cycle delay. Try turning them off. Those delay-cycles are ease to verify in the last Tab of block memory generator. 

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Observer
Observer
1,129 Views
Registered: ‎05-09-2018
i initialized my instruction BRAM by .coe file and added .mif file, blk mem gen.v source file in my directory
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Adventurer
Adventurer
1,297 Views
Registered: ‎05-23-2018

Per default, in block memory generator the output registers are active, which cause an additional cycle delay. Try turning them off. Those delay-cycles are ease to verify in the last Tab of block memory generator. 

View solution in original post

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Observer
Observer
1,087 Views
Registered: ‎05-09-2018

you are right. i tested without output reg, test result is correct.

thank you very much :)

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