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We have configured a system where the FPGA and the ARM accesses the same OCM memory through AXI3. This works flawlessly. However, when we use the D-Stream JTAG debugger and debug the ARM through DS5, the FPGA cannot read the OCM data correctly. We have checked the AXI3 communication on the FPGA, and all read/write accesses completes correctly. But we can see that the data read by the FPGA during debugging is invalid.
We have tried several things to solve the problem; one that had some effect is if we hold back the AXI3 communication during startup, and then reduce the amount of data being communicated. But as soon as the amount of data rises the FPGA starts to misread the data, and it’s not possible to reestablish the communication even though that all read/writes are reported successfully through the AX3 interface.
When initiating the debug a “reset system” is performed and the FSBL is loaded. So the complete system should be reset correctly when debugging. It’s also possible to debug the ARM with single stepping, register access etc. So we only experience a problem with the OCM as described above.