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[Route 35-54] Net: twoTx3GoneRx1dot5G_support_i/co... - ( ‎01-11-2021 12:54 AM )

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Re: ZCU102 IBERT 10Gb Line Rate with Mhz reference... - ( ‎12-28-2020 03:58 AM )

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FSBL and GTH lock - ( ‎12-11-2020 01:44 AM )

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What is the dependency among lane data rate, PRBS ... - ( ‎10-28-2020 11:13 AM )

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9 Replies 731 Views

HDMI and 10GbE - ( ‎10-26-2020 01:53 AM )

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11 Replies 977 Views

GTH recovered clock issue with HDMI - ( ‎09-28-2020 02:30 PM )

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Kintex ultrascale GTH RX - Power Spliiter (SFP inp... - ( ‎09-17-2020 12:03 AM )

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DVPPIN vs BER Eye Mask - ( ‎09-04-2020 10:46 AM )

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4 Replies 499 Views

GTH Rx margin analysis - ( ‎07-29-2020 01:39 AM )

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Re: GTH QPLL frequency range - ( ‎07-22-2020 02:37 PM )

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GTH rx_cdrlok_out signal - ( ‎07-21-2020 05:41 AM )

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Aurora 64b/66b Slave does not lock, no channel/lan... - ( ‎06-03-2020 07:51 PM )

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IO standards for Aurora/GTH Tx/Rx pins? - ( ‎05-10-2020 10:18 PM )

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GTH Transceiver reference clock requirement - ( ‎05-07-2020 05:56 AM )

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Re: XCKU085 GTH generate wrong rxusrclk2 - ( ‎04-29-2020 05:11 AM )

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Re: XCKU085 GTH generate wrong rxusrclk2 - ( ‎04-29-2020 04:31 AM )

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UHD-SDI GT txoutclk broken - ( ‎04-07-2020 04:32 PM )

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Debugging Aurora 64b66b when PLL is not locking (X... - ( ‎03-22-2020 09:51 PM )

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GTH package delay - ( ‎03-05-2020 10:20 AM )

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Byte alignment at synchronous Ethernet (SyncE) and... - ( ‎03-05-2020 05:27 AM )

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Multi-lane GTX Transmitter Alignment - ( ‎02-27-2020 12:30 PM )

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UltraScale+ GTH AMI Rx Contour Mask - ( ‎01-13-2020 05:45 AM )

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UltraScale+ GTH IBIS-AMI Simulation for PCIe - ( ‎01-13-2020 05:39 AM )

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编译错误 vivado 12-1411 - ( ‎11-27-2019 05:45 AM )

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Vivado [12-1411] - ( ‎11-27-2019 05:29 AM )

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Eye Scan on GTH on VCU108 under MicroBlaze Control - ( ‎10-25-2019 06:51 PM )

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Auroa 64/66 Zync Ultrascale+ lane GTH Assignment - ( ‎09-26-2019 08:33 AM )

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GTH QPLL valid N values - ( ‎08-20-2019 09:34 AM )

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XAPP 1198 targetting UltraScale (XCVU095-FFVB2104E... - ( ‎08-14-2019 04:13 PM )

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Re: Ultrascale+ GTH RX Phase Interpolator - ( ‎07-20-2019 02:09 PM )

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Ultrascale GTH Dynamic Change - ( ‎06-28-2019 06:24 AM )

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Re: GTH LOC issue on Kintex Ultrascale - ( ‎06-17-2019 12:55 PM )

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Data output on transceiver TX pins jitters or drif... - ( ‎06-06-2019 11:52 AM )

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HDMI GTH pin swap - ( ‎05-28-2019 05:53 AM )

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FMC GTH Clock output - ( ‎05-21-2019 03:28 AM )

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GTX transceiver in Kintex Ultrascale - ( ‎04-30-2019 03:02 PM )

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Snooping a GTH IO pad and output it to a pad - ( ‎04-02-2019 03:37 PM )

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PcsPma IP core from tcl - ( ‎02-11-2019 10:37 AM )

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IBERT on VCU108 - ( ‎11-08-2018 11:49 PM )

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Pairing Ultrascale GTH with a QSFP range extender - ( ‎10-11-2018 11:14 PM )

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JESD204B Multibank Clock Sharing - ( ‎08-20-2018 11:42 AM )

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UltraScale+ GTH Reset (Configuration) Failure - RX... - ( ‎07-25-2018 07:38 AM )

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RapidIO at 3.125Gbps can't link smoothly between X... - ( ‎07-16-2018 12:04 AM )

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hdmi 2.0 IP on virtex 7 GTH - ( ‎07-15-2018 06:46 PM )

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Configuring 7 series FPGA Transceiver wizard for V... - ( ‎06-13-2018 06:35 AM )

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Xilinx Virtex7 XC7V2000TFLG1925-1 PCIe Phy PIPE mo... - ( ‎06-04-2018 03:28 PM )

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GTHE3_CHANNEL character alignment RX_SLIDE issue. - ( ‎05-23-2018 08:11 AM )

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US/US+ GTH/GTY XCVR SSC RX OUtput Clock Behavior - ( ‎03-07-2018 03:28 PM )

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3 Replies 1417 Views

Re: Video Phy Configuration for Displayport RX Sub... - ( ‎02-28-2018 05:40 AM )

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GTH CPRI implementation issue - ( ‎01-15-2018 06:33 AM )

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14 Replies 3551 Views