Top Tagged

xpm_fifo_sync read/write counts - ( ‎08-13-2018 12:53 PM )

by on Latest post on by

2 Replies 1545 Views

Simultaneous FIFO read-write with Independent RD a... - ( ‎08-08-2018 08:36 PM )

by on Latest post on by

3 Replies 2419 Views

Error when simulating Xilinx block memory based FI... - ( ‎06-15-2018 05:49 AM )

by on Latest post on by

2 Replies 1238 Views

AXI Stream to DDR via FiFo by AXI_DMA - ( ‎06-08-2018 03:33 AM )

by on Latest post on by

2 Replies 1334 Views

XPM_FIFO Macros' Resetting - ( ‎02-10-2018 06:30 PM )

by on Latest post on by

2 Replies 1831 Views

FIFO Differences - ( ‎02-09-2018 06:48 PM )

by on Latest post on by

3 Replies 1881 Views

Independent 18Kb FIFOs - ( ‎02-09-2018 06:47 PM )

by on Latest post on by

2 Replies 1224 Views

Zynq (PS) - AXI - FPGA (PL), AXI 4 Stream Intercon... - ( ‎02-08-2018 11:29 AM )

by on Latest post on by

4 Replies 2499 Views

Re: Built-in Asynchronous FIFO Error Rate - ( ‎02-05-2018 01:23 PM )

by on

2 Replies 1679 Views

Built-in Asynchronous FIFO Error Rate - ( ‎02-04-2018 08:47 PM )

by on Latest post on by

4 Replies 1724 Views

Non-symmetrical aspect ratio in BRAM FIFO on Z7C70... - ( ‎01-10-2018 06:40 AM )

by on Latest post on by

2 Replies 1434 Views

Re: AXI4-Stream module in custom IP [How to use?] - ( ‎11-06-2017 11:06 PM )

by on

2 Replies 10935 Views

Re: xapp585 cameralink protocol first line pixel s... - ( ‎11-06-2017 10:52 PM )

by on

1 Reply 2050 Views

Re: AXI4-Stream module in custom IP [How to use?] - ( ‎11-03-2017 01:50 PM )

by on

4 Replies 11016 Views

Re: [IP_Flow 19-3389] Failed to import IP file. ( ... - ( ‎11-02-2017 02:32 PM )

by on

0 Replies 2288 Views

[IP_Flow 19-3389] Failed to import IP file. ( simu... - ( ‎11-02-2017 12:22 AM )

by on Latest post on by

3 Replies 2335 Views

Axi-Stream Interface timing - ( ‎11-01-2017 04:23 AM )

by on Latest post on by

5 Replies 2988 Views

xapp585 cameralink protocol first line pixel shift... - ( ‎10-30-2017 02:54 PM )

by on Latest post on by

5 Replies 2148 Views

Why using FIFO ?? - ( ‎09-15-2017 02:14 AM )

by on Latest post on by

3 Replies 2210 Views

What type of storage unit is better to use in cont... - ( ‎08-22-2017 11:59 PM )

by on Latest post on by

2 Replies 2141 Views

Re: Timing met errors in place and route simulatio... - ( ‎07-21-2017 10:52 AM )

by on

0 Replies 3104 Views

Re: FIFOs loose coherency - ( ‎07-21-2017 05:03 AM )

by on

1 Reply 8484 Views

Re: FIFOs loose coherency - ( ‎07-20-2017 01:36 PM )

by on

3 Replies 5738 Views

Explain the use of FIFO for passing array to H/W f... - ( ‎06-12-2017 04:09 AM )

by on

0 Replies 2145 Views

Re: Implementing programmable delay in fifo - ( ‎05-16-2017 01:55 PM )

by on

1 Reply 2888 Views

Re: FIFO not reading data. - ( ‎05-15-2017 05:01 AM )

by on

1 Reply 2813 Views

Check FIFO occupancy from PL? - ( ‎05-12-2017 08:11 AM )

by on Latest post on by

11 Replies 5802 Views

Re: can I build small (undeep) fifo's using FIFO_S... - ( ‎04-21-2017 09:20 AM )

by on

6 Replies 5571 Views

Re: Helping to Meet Timing on the Reset of a FIFO ... - ( ‎10-05-2016 06:04 AM )

by on

0 Replies 6918 Views

Re: Helping to Meet Timing on the Reset of a FIFO ... - ( ‎10-04-2016 11:01 AM )

by on

2 Replies 6955 Views

Re: Helping to Meet Timing on the Reset of a FIFO ... - ( ‎10-03-2016 01:15 PM )

by on

4 Replies 6992 Views

Re: General approach on using FIFOs - ( ‎09-22-2016 01:12 PM )

by on

2 Replies 5447 Views

Syntax error while defining signal of type record - ( ‎09-20-2016 07:37 AM )

by on

0 Replies 2957 Views

FIFO generator issue - ( ‎07-25-2016 07:27 AM )

by on Latest post on by

2 Replies 4289 Views

how can I handle about AXI4-Lite Mapped to FIFO s_... - ( ‎07-16-2016 04:07 AM )

by on Latest post on by

2 Replies 4330 Views

Use FIFO in HLS design - ( ‎06-28-2016 02:58 AM )

by on Latest post on by

2 Replies 7141 Views

Synthesize a zero depth FIFO using HLS - ( ‎10-30-2015 04:35 PM )

by on Latest post on by

5 Replies 9835 Views

Zynq Ethernet Receive DMA bug - ( ‎08-06-2015 12:24 PM )

by on

0 Replies 6705 Views

Synchronizing Multiple AXI Data Streams thru Combi... - ( ‎07-21-2015 03:34 PM )

by on Latest post on by

2 Replies 8677 Views

change fsl fifo depth error - ( ‎11-18-2014 02:09 PM )

by on Latest post on by

4 Replies 6254 Views

BRAM instead of nativ FIFO used - ( ‎09-17-2014 02:47 AM )

by on

0 Replies 8154 Views

using synplify for synthesis from within ISE 14.5 ... - ( ‎06-27-2014 06:05 PM )

by on Latest post on by

1 Reply 3271 Views

Actual Read/Write Width FIFO Generator v9.3 questi... - ( ‎01-21-2014 11:17 AM )

by on Latest post on by

4 Replies 10641 Views

Cannot add fifo.ngc file to my top module - ( ‎01-02-2014 03:23 AM )

by on Latest post on by

7 Replies 11149 Views

No output from FIFO - ( ‎12-05-2013 10:20 PM )

by on Latest post on by

5 Replies 13322 Views

FIFO36 Almost_full stuck bit simulation - ( ‎09-06-2013 03:58 AM )

by on Latest post on by

11 Replies 8124 Views

Re: Vivado HLS - AXI4 Stream FIFO - ( ‎06-22-2013 05:27 AM )

by on

4 Replies 13488 Views

XPS Mailbox FIFO depth - ( ‎05-07-2013 01:44 AM )

by on

0 Replies 1799 Views

Kernel with FSL - ( ‎02-11-2013 05:51 PM )

by on

0 Replies 1727 Views