Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Solutions
Products
Support
Account
My Account
Create Account
Sign Out
Search
All
Silicon Devices
Boards and Kits
Intellectual Property
Support
Documentation
Knowledge Base
Community Forums
Partners
Videos
Press
Search
Browse
Sign In
Help
Tag: "PAR"
All community
Users
cancel
Turn on suggestions
Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.
Showing results for
Show
only
|
Search instead for
Did you mean:
Community Forums
:
Tag: "PAR"
Options
Delete this tag for Anonymous everywhere
Replace this tag for Anonymous everywhere
Tag: "PAR"
20 posts
|
13 taggers
|
First used:
03-10-2009
Latest Tagged
DDR3 placement and route (PAR) error for artix 7
- (
09-10-2017
08:41 PM
)
Memory Interfaces and NoC
by
maheen_189
on
09-10-2017
08:41 PM
Latest post on
09-21-2017
07:33 PM
by
kren
2
Replies
1335
Views
2
Replies
1335
Views
DDR3 placement and route error for artix 7
- (
08-17-2017
11:22 PM
)
Memory Interfaces and NoC
by
maheen_189
on
08-17-2017
11:22 PM
Latest post on
08-27-2017
08:31 PM
by
maheen_189
8
Replies
4176
Views
8
Replies
4176
Views
Re: Suppress "ERROR:PhysDesignRules:1709 - Incompl...
- (
07-26-2016
09:50 PM
)
Implementation
by
Anonymous
on
07-26-2016
09:50 PM
0
Replies
7561
Views
0
Replies
7561
Views
"max. freq" of a design ...
- (
10-13-2014
12:36 AM
)
Timing Analysis
by
zubin_kumar31
on
10-13-2014
12:36 AM
Latest post on
10-13-2014
10:09 AM
by
zubin_kumar31
2
Replies
9372
Views
2
Replies
9372
Views
reg: without changing RTL, resolving setup violati...
- (
10-12-2014
04:33 PM
)
Timing Analysis
by
zubin_kumar31
on
10-12-2014
04:33 PM
Latest post on
10-14-2014
01:51 PM
by
hgleamon1
9
Replies
13587
Views
9
Replies
13587
Views
Xilinx reports high Fmax, but cant PAR for a lower...
- (
10-09-2014
01:22 PM
)
Timing Analysis
by
zubin_kumar31
on
10-09-2014
01:24 PM
0
Replies
6455
Views
0
Replies
6455
Views
timing score = 0, all constraints met, but .twx re...
- (
10-08-2014
07:04 PM
)
General Technical Discussion
by
zubin_kumar31
on
10-08-2014
07:04 PM
Latest post on
10-15-2014
10:12 AM
by
zubin_kumar31
1
Reply
5602
Views
1
Reply
5602
Views
hold time violations in MAP report but PAR report ...
- (
12-20-2013
06:34 AM
)
General Technical Discussion
by
zubin_kumar31
on
12-20-2013
06:34 AM
Latest post on
12-20-2013
01:37 PM
by
zubin_kumar31
8
Replies
7706
Views
8
Replies
7706
Views
Post Place and Route simulation with MicroBlaze
- (
09-11-2013
01:34 AM
)
Embedded Development Tools
by
lucianocapasso
on
09-11-2013
01:34 AM
Latest post on
10-07-2013
06:41 AM
by
lucianocapasso
32
Replies
9005
Views
32
Replies
9005
Views
ISE PAR: Intermediate hold violations, are they ha...
- (
04-11-2013
11:39 PM
)
Implementation
by
Anonymous
on
04-11-2013
11:39 PM
Latest post on
04-28-2013
11:44 PM
by
Anonymous
4
Replies
7710
Views
4
Replies
7710
Views
View All ≫
Top Tagged
DDR3 placement and route (PAR) error for artix 7
- (
09-10-2017
08:41 PM
)
Memory Interfaces and NoC
by
maheen_189
on
09-10-2017
08:41 PM
Latest post on
09-21-2017
07:33 PM
by
kren
2
Replies
1335
Views
2
Replies
1335
Views
DDR3 placement and route error for artix 7
- (
08-17-2017
11:22 PM
)
Memory Interfaces and NoC
by
maheen_189
on
08-17-2017
11:22 PM
Latest post on
08-27-2017
08:31 PM
by
maheen_189
8
Replies
4176
Views
8
Replies
4176
Views
Re: Suppress "ERROR:PhysDesignRules:1709 - Incompl...
- (
07-26-2016
09:50 PM
)
Implementation
by
Anonymous
on
07-26-2016
09:50 PM
0
Replies
7561
Views
0
Replies
7561
Views
"max. freq" of a design ...
- (
10-13-2014
12:36 AM
)
Timing Analysis
by
zubin_kumar31
on
10-13-2014
12:36 AM
Latest post on
10-13-2014
10:09 AM
by
zubin_kumar31
2
Replies
9372
Views
2
Replies
9372
Views
reg: without changing RTL, resolving setup violati...
- (
10-12-2014
04:33 PM
)
Timing Analysis
by
zubin_kumar31
on
10-12-2014
04:33 PM
Latest post on
10-14-2014
01:51 PM
by
hgleamon1
9
Replies
13587
Views
9
Replies
13587
Views
Xilinx reports high Fmax, but cant PAR for a lower...
- (
10-09-2014
01:22 PM
)
Timing Analysis
by
zubin_kumar31
on
10-09-2014
01:24 PM
0
Replies
6455
Views
0
Replies
6455
Views
timing score = 0, all constraints met, but .twx re...
- (
10-08-2014
07:04 PM
)
General Technical Discussion
by
zubin_kumar31
on
10-08-2014
07:04 PM
Latest post on
10-15-2014
10:12 AM
by
zubin_kumar31
1
Reply
5602
Views
1
Reply
5602
Views
hold time violations in MAP report but PAR report ...
- (
12-20-2013
06:34 AM
)
General Technical Discussion
by
zubin_kumar31
on
12-20-2013
06:34 AM
Latest post on
12-20-2013
01:37 PM
by
zubin_kumar31
8
Replies
7706
Views
8
Replies
7706
Views
Post Place and Route simulation with MicroBlaze
- (
09-11-2013
01:34 AM
)
Embedded Development Tools
by
lucianocapasso
on
09-11-2013
01:34 AM
Latest post on
10-07-2013
06:41 AM
by
lucianocapasso
32
Replies
9005
Views
32
Replies
9005
Views
ISE PAR: Intermediate hold violations, are they ha...
- (
04-11-2013
11:39 PM
)
Implementation
by
Anonymous
on
04-11-2013
11:39 PM
Latest post on
04-28-2013
11:44 PM
by
Anonymous
4
Replies
7710
Views
4
Replies
7710
Views
View All ≫
Top Taggers
Member
Count
zubin_kumar31
5
mehrdadfeller
2
vizziee
2
maheen_189
2
evgenis1
1
View All ≫
View Tagging Leaderboards for Community
