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jisu
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About jisu
Latest posts by jisu
Subject
Views
Posted
Re: LUT, BRAM, Register
Other FPGA Architecture
492
08-19-2020
01:25 AM
Resource Area of ZCU106 FPGA platform
Implementation
417
06-23-2020
10:19 PM
Re: Pragma about FMul_fulldsp and FAddSub_fulldsp
High-Level Synthesis (HLS)
985
05-20-2019
05:50 PM
Pragma about FMul_fulldsp and FAddSub_fulldsp
High-Level Synthesis (HLS)
1024
05-19-2019
08:49 PM
[Route 35-162] Route error in vivado 2018.3.
Implementation
710
05-16-2019
12:59 AM
View All ≫
My Accepted Solutions
Subject
Views
Posted
Re: Synthesis error in Vivado HLS: Abnormal progra...
High-Level Synthesis (HLS)
881
05-13-2019
11:13 PM
Re: Cannot change the frequency governor on zynq b...
Processor System Design and AXI
560
02-26-2019
10:12 PM
View All ≫
Community Statistics
Posts
32
Solutions
2
Kudos given
0
Kudos received
0
Member Since
07-02-2018
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Date Last Visited
08-19-2020
04:47 AM
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