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fmueck
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About fmueck
Latest posts by fmueck
Subject
Views
Posted
Re: DDR sysclk input circuit, UGs disagree
Memory Interfaces and NoC
293
05-13-2020
06:24 AM
DDR sysclk input circuit, UGs disagree
Memory Interfaces and NoC
317
05-13-2020
04:46 AM
Re: A7 MIG4.2 custom 72b 1.35V 312.5MHz calib_comp...
Memory Interfaces and NoC
306
04-07-2020
11:50 PM
Re: A7 MIG4.2 custom 72b 1.35V 312.5MHz calib_comp...
Memory Interfaces and NoC
459
03-25-2020
06:34 AM
A7 MIG4.2 custom 72b DDR3 calib_complete but incoh...
Memory Interfaces and NoC
461
03-25-2020
06:32 AM
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Member Since
09-19-2018
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Date Last Visited
05-13-2020
09:44 AM
Latest Tags
artix 7
clock input
ddr
DDR3
mig
sysclk
termination
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