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bfung_2
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About bfung_2
Latest posts by bfung_2
Subject
Views
Posted
Simulation of SelectIO LVDS SERDES of Zynq FPGA
Other FPGA Architecture
80
07-20-2021
06:22 PM
ERROR:sim - Failed to generate 'u_icon_CV'. Faile...
Vivado Debug and Power Estimation Tools
112
07-08-2021
05:55 PM
Re: Shared interrupt (IRQ_F2P[15:0]) is level trig...
Embedded Linux
173
05-20-2021
10:30 PM
Re: Shared interrupt (IRQ_F2P[15:0]) is level trig...
Embedded Linux
207
05-20-2021
03:37 PM
Re: Correct Interrupt IRQ Acknowledge from Petalin...
Embedded Linux
127
05-19-2021
12:05 PM
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My Accepted Solutions
Subject
Views
Posted
Re: Petalinux Config from 1 GiB to 4 GiB DRAM
Embedded Linux
181
04-13-2021
12:33 PM
Re: Modify Boot.Scr to set ethaddr
Embedded Linux
478
03-18-2021
09:01 PM
Re: Petalinux 2020.1 NFS Root FS Boot
Embedded Linux
463
03-01-2021
05:50 PM
Re: kernel module source include file in petalinux
Embedded Linux
433
12-03-2020
04:42 PM
Re: 7-series GTX IBERT Example Design @ 0.625 Gbps
Serial Transceivers
556
11-16-2020
05:08 PM
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Community Statistics
Posts
69
Solutions
6
Kudos given
34
Kudos received
1
Member Since
07-02-2020
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Offline
Date Last Visited
07-22-2021
04:09 PM
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anatoli
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isaacjt
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fsqinematiq
1
JPK17
2
stephenm
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Latest Tags
petalinux
ZYNQ
Vivado
boot
ddr
DEBUG
device tree
DMA
dram
kernel
LVDS
QEMU
rootfs
u-boot
2020.1
agentx
boot count
burst
chipscope
Differential
driver
dsp
dtb
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edk
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file systems
gtx
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