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Xilinx Employee

Latest posts by hobson

Subject

Views

Posted

Re: timing constaint: TS RXIN_generic_ethernet_10_...

3367

‎03-25-2010 09:02 AM

Re: About Timing errors in Post route simulation i...

9707

‎03-25-2010 08:56 AM

Re: Bit vectors and FPGA output pins

16296

‎03-16-2010 01:39 PM

Re: Post-Route Simulation

5917

‎03-16-2010 01:18 PM

Re: Floorplan Error

9891

‎03-16-2010 11:47 AM

My Accepted Solutions

Subject

Views

Posted

Re: Bit vectors and FPGA output pins

16296

‎03-16-2010 01:39 PM

Re: OFFSET IN DDR timing constraints....again.....

15877

‎11-19-2009 09:48 AM

Re: What is the correct way to constrain an interf...

7566

‎09-08-2009 03:45 PM

Re: How to constrain a path from internal register...

11094

‎08-22-2009 06:29 AM

Community Stats

Posts	58
Solutions	6
Kudos Given	0
Kudos Received	12
Member Since	‎04-15-2008

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