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primoz_beltram
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About primoz_beltram
Latest posts by primoz_beltram
Subject
Views
Posted
Bug in xapp1175 reference design file xilskey_efus...
Processor System Design and AXI
106
07-02-2021
07:19 AM
Vitis IDE makefile project and "Build directory:" ...
Embedded Development Tools
185
05-13-2021
04:50 AM
Re: Petalinux 2020.2 can not change DEFAULT_TIMEZO...
Embedded Linux
164
04-28-2021
02:02 AM
Petalinux 2020.2 can not change DEFAULT_TIMEZONE f...
Embedded Linux
238
04-27-2021
10:46 AM
Re: Debug Kernel / Kernel driver
Embedded Linux
175
02-24-2021
09:15 AM
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My Accepted Solutions
Subject
Views
Posted
Re: Petalinux FSBL source code
Embedded Development Tools
1094
09-14-2020
07:50 AM
Re: Clocks in device tree
Embedded Linux
1513
02-02-2020
06:58 AM
Re: Enabling/disabling FCLK_CLKx at runtime in Pet...
Embedded Linux
1371
06-04-2019
07:08 AM
Re: UltraScale+ system monitor
Vivado Debug and Power Estimation Tools
1452
03-14-2019
09:13 AM
Re: AD-FMCOMMS4-EBZ with Xilinx Artix-7 FPGA AC701...
Vivado TCL Community
1310
01-10-2019
10:43 AM
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Community Statistics
Posts
159
Solutions
11
Kudos given
16
Kudos received
43
Member Since
02-22-2012
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Date Last Visited
07-13-2021
03:03 PM
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