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daniel.cogan
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About daniel.cogan
Latest posts by daniel.cogan
Subject
Views
Posted
Can the HDMI transmitter subsystem IP be used with...
Video and Audio
131
04-05-2021
12:36 PM
Re: How can I make the first and last few rows and...
High-Level Synthesis (HLS)
225
01-29-2021
08:11 AM
Re: How can I make the first and last few rows and...
High-Level Synthesis (HLS)
283
01-28-2021
08:57 AM
It won't parallelize
High-Level Synthesis (HLS)
258
01-28-2021
08:31 AM
IP Sharing
High-Level Synthesis (HLS)
174
01-25-2021
01:30 PM
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My Accepted Solutions
Subject
Views
Posted
Re: HLS Debugger error
High-Level Synthesis (HLS)
485
09-25-2020
06:00 AM
Re: LUTs per SLR
Versal and UltraScale Architecture™
549
08-21-2019
10:29 AM
Re: Why didn't external VREF work?
Other FPGA Architecture
9056
01-12-2017
10:36 AM
Re: lpddr2 example design doesn't calibrate
Other FPGA Architecture
7101
01-09-2017
04:48 PM
Re: multiport lpddr2 on Artix-7
Memory Interfaces and NoC
11088
11-04-2013
01:53 PM
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Community Statistics
Posts
141
Solutions
5
Kudos given
28
Kudos received
11
Member Since
07-30-2013
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Date Last Visited
04-05-2021
07:35 PM
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