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steve_farmer
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About steve_farmer
Latest posts by steve_farmer
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Re: write_vhdl vs. write_verilog
Welcome & Join
62
05-28-2020
02:07 AM
Keep multi-dimensional arrays from generate of mul...
Simulation and Verification
101
05-27-2020
05:03 PM
axi4stream_vip_v1_0 randomize Tvalid outputs on Ma...
Simulation and Verification
126
04-12-2020
04:56 PM
Re: Debugging systemverilog classes with Vivado
Simulation and Verification
156
03-26-2020
05:44 PM
Re: UVM Testbench Simulation Stops 2019.2
Simulation and Verification
364
01-31-2020
05:33 PM
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My Accepted Solutions
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Re: UVM Testbench Simulation Stops 2019.2
Simulation and Verification
364
01-31-2020
05:33 PM
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06:27 AM
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