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andreforme
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About andreforme
Latest posts by andreforme
Subject
Views
Posted
Re: reset PL from PS using FPGA_RST_CTRL register
Processor System Design and AXI
13100
05-24-2016
08:08 AM
reset PL from PS using FPGA_RST_CTRL register
Processor System Design and AXI
7416
05-24-2016
06:40 AM
Re: Zynq ARM embedded assembly problem
Processor System Design and AXI
11498
04-20-2016
02:32 AM
Zynq ARM embedded assembly problem
Processor System Design and AXI
6195
04-18-2016
03:58 AM
Input data timing problem
Processor System Design and AXI
8249
03-17-2016
09:12 AM
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My Accepted Solutions
Subject
Views
Posted
Re: reset PL from PS using FPGA_RST_CTRL register
Processor System Design and AXI
13100
05-24-2016
08:08 AM
Re: Zynq ARM embedded assembly problem
Processor System Design and AXI
11498
04-20-2016
02:32 AM
Re: PS to PL interrupt on Zynq
Processor System Design and AXI
10675
07-28-2015
06:30 AM
Re: Zynq DMA transfer Performance
Processor System Design and AXI
13257
03-24-2015
02:35 AM
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Community Statistics
Posts
16
Solutions
4
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0
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Member Since
03-04-2015
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Online Status
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Date Last Visited
05-24-2016
11:29 AM
Latest Tags
custom IP
DMA
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