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jianmingli1
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About jianmingli1
Latest posts by jianmingli1
Subject
Views
Posted
axi4-lite and axi4-stream in one IP
Processor System Design and AXI
818
12-05-2017
02:05 AM
Re: Vivado timing check warning
Timing Analysis
1835
10-28-2017
04:43 AM
Vivado timing check warning
Timing Analysis
1847
10-28-2017
04:13 AM
Re: estimated clock
High-Level Synthesis (HLS)
2105
10-23-2017
07:20 AM
Re: estimated clock
High-Level Synthesis (HLS)
3039
10-23-2017
02:41 AM
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My Accepted Solutions
Subject
Views
Posted
Re: SDK test data issue
High-Level Synthesis (HLS)
1241
10-07-2017
06:17 AM
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Community Stats
Posts
71
Solutions
1
Kudos Given
31
Kudos Received
4
Member Since
07-09-2017
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Date Last Visited
02-27-2018
03:23 AM
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